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1 copyright ? cirrus logic, inc. 2006 (all rights reserved) www.cirrus.com cs4954 cs4955 ntsc/pal digital video encoder features z six dacs providing simultaneous composite,s-video, and rgb or component yuv outputs z programmable dac output currents for low impedance (37.5 ) and high impedance (150 ) loads z multi-standard support for ntsc-m, ntsc- japan, pal (b, d, g, h, i, m, n, combination n) z itu r.bt656 input mode supporting eav/sav codes and ccir6 01 master/slave input modes z programmable hsync and vsync timing z multistandard teletext (europe, nabts, wst) support z vbi encoding support z wide-screen signaling (wss) support, eia-j cpx1204 z ntsc closed caption encoder with interrupt z cs4955 supports macrovision copy protection version 7 z host interfac e configurable for parallel or i2c ? compatible operation z on-chip voltage reference generator z +3.3 v or +5 v operation, cmos, low-power modes, three-state dacs description the cs4954/5 provides full conversion from digital video formats ycbcr or yuv to ntsc and pal composite, y/c (s-video) and rgb, or yuv analog video. input for- mats can be 27 mhz 8-bit yuv, 8-bit ycbcr, or itu r.bt656 with support for eav/ sav codes. video output can be formatted to be comp atible with ntsc-m, ntsc- j, pal-b,d,g,h,i,m,n, and combination n systems. closed caption is supported in ntsc. teletext is sup- ported for ntsc and pal. six 10-bit dacs provide two channels for an s-video output port, one or two composite video outputs, and three rgb or yuv outputs. two-times oversampling re- duces the output filter requirements and guarantees no dac-related modulation co mponents within the speci- fied bandwidth of any of the supported video standards. parallel or high-speed i2c comp atible control interfaces are provided for flexibility in system design. the parallel interface doubles as a general purpose i/o port when the cs4954/5 is in i2c mode to help conserve valuable board area. the cs4954 and cs4955 are available in a 48-pin tqfp and operate in -40 to +85c ambient temperature. the cdb4954/55 customer demonstration board is also available. please refer to ?ordering information? on page 2 . september '06 ds278f6 clk iset dgnd scl sda pdat[7:0] rd wr padr xtal_out vd[7:0] hsync vsync field int reset i2c interface host parallel interface color sub-carrier synthesizer 8 video formatter control registers chroma modulate chroma amplifier output interpolate lpf burst insert chroma interpolate lpf luma interpolate luma amplifier sync insert u,v y video timing generator test current reference voltage reference vref r dac y dac cvbs dac c 10-bit dac vaa xtal_in teletext encoder ttxrq ttxdat ycbcr to rbg b dac g dac 10-bit 10-bit 10-bit 10-bit 10-bit rgb rgb y y 8 color space converter
cs4954 cs4955 2 ds278f6 ordering information product description package pb-free grade temp range container order# cs4954 ntsc/pal digital video encoder 48-tqfp yes commercial -40o to +85oc rail cs4954-cqz cs4955 CS4955-CQZ cdb4954/55 cs4954/55 evaluation board no - - - cdb4954a/55a
cs4954 cs4955 ds278f6 3 table of contents 1. characteristics and specifications . .............. .............. .............. .............. ............ ........... ........6 ac & dc parametric specifications ... .............. .............. .............. .............. .............. ........... ........6 recommended operating conditions .............................................................................................. .........6 thermal characteristics ....................................................................................................... .......6 dc characteristics ............................................................................................................ ..............6 ac characteristics ............................................................................................................ ..............8 timing characteristics ........................................................................................................ ...........9 2. additional cs4954/5 features ........ .............. .............. .............. .............. ........... ............ ......... .....11 3. cs4954 introduction ..... .............. .............. .............. .............. ............ ........... ........... .......... .............11 4. functional description ...................................................................................................... .........11 4.1 video timing generato r ..................................................................................................... ..........11 4.2 video input formatter .......... ............................................................................................ ............12 4.3 color subcarrier synthesizer ............................................................................................... ........12 4.4 chroma path ................................................................................................................ ................12 4.5 luma path .................................................................................................................. ..................13 4.6 rgb path and component yuv path .............. .............. .............. .............. .............. ........... .........13 4.7 digital to analog converters ...................... ......................................................................... .........13 4.8 voltage reference ............... ........................................................................................... .............14 4.9 current reference ................ .......................................................................................... ..............14 4.10 host interface ............................................................................................................ ...................14 4.11 closed caption services ................................................................................................... ...........14 4.12 teletext services ......................................................................................................... .................15 4.13 wide-screen signaling support and cgms ................................................................................15 4.14 vbi encoding .............................................................................................................. .................15 4.15 control registers ......................................................................................................... ................15 4.16 testability ............................................................................................................... ......................15 5. operational description ..................................................................................................... .......15 5.1 reset hierarchy ............................................................................................................ ...............15 5.2 video timing ............................................................................................................... .................16 5.2.1 slave mode input interface ............................................................................................... 16 5.2.2 master mode input interface ......................... ....................................................................1 6 5.2.3 vertical timing .......................................................................................................... .........17 5.2.4 horizontal timing ........................................................................................................ ......17 5.2.5 ntsc interlaced .......................................................................................................... ......17 5.2.6 pal interlaced ........................................................................................................... ........17 5.2.7 progressive scan ......................................................................................................... .....18 5.2.8 ntsc progressive scan ...................................................................................................1 8 5.2.9 pal progressive scan ............................... ...................................................................... .19 5.3 itu-r.bt656 ................................................................................................................ ................19 5.4 digital video input modes .................................................................................................. ..........21 5.5 multi-standard output format m odes .............. .............. .............. .............. ........... ........... ........... .21 5.6 subcarrier generation ...................................................................................................... ............22 5.7 subcarrier compensation ......... .............. .............. .............. .............. .............. ............ ......... ........23 5.8 closed caption insertion ................................................................................................... ...........23 5.9 programmable h-sync and v-sync ....................... ...................................................................... .24 5.10 wide screen signaling (wss) and cgms ..................................................................................24 5.11 teletext support ..... .............. .............. .............. .............. ........... ........... ........... ............ .................24 5.12 color bar generator ............. .............. .............. .............. .............. ........... ........... ............ ..............26 5.13 vbi encoding .............................................................................................................. ..................27 5.14 super white/super black suppor t .............. .............. .............. .............. .............. ............ ......... .....27 5.15 interrupts ................................................................................................................ ......................27 5.16 general purpose i/o port .................................................................................................. ...........27 6. filter responses ... .............. .............. .............. .............. .............. .............. ........... .......... ................29 7. analog ............... .............. .............. .............. .............. .............. ........... ........... ........... ..........................32 7.1 analog timing .............................................................................................................. ................32 7.2 vref ....................................................................................................................... .....................32 7.3 iset ....................................................................................................................... ......................32 7.4 dacs ....................................................................................................................... .....................32 7.4.1 luminance dac ............................................................................................................ ....32 7.4.2 chrominance dac ....... .............. .............. .............. .............. ........... ........... ........... .......... ..33 7.4.3 cvbs dac .......... .............. .............. .............. .............. .............. ........... ............ .......... .......33 7.4.4 red dac .................................................................................................................. .........33
cs4954 cs4955 4 ds278f6 7.4.5 green dac ................................................................................................................ ....... 33 7.4.6 blue dac ................................................................................................................. ......... 33 7.4.7 dac useage rules ......................................................................................................... .. 34 8. programming ................................................................................................................. .................. 34 8.1 host control interface ..................................................................................................... ............. 34 8.1.1 i2c? interface ........................................................................................................... ........ 34 8.1.2 8-bit parallel interface ... .............................................................................................. ...... 35 8.2 register description ....................................................................................................... ............. 36 8.2.1 control registers ........................................................................................................ ...... 36 9. board design and layout conside rations ............ .............. .............. .............. ........... ........ 53 9.1 power and ground planes .................................................................................................... ...... 53 9.2 power supply decoupling ....... ............................................................................................. ....... 53 9.3 digital interconnect ............ .............. .............. .............. .............. .............. ........... .......... ............... 53 9.4 analog interconnect ........................................................................................................ ............. 53 9.5 analog output protection ................................................................................................... ......... 54 9.6 esd protection ............................................................................................................. ............... 54 9.7 external dac output filter ................................................................................................. ......... 54 10. pin description ........................................................................................................... .................... 56 11. package drawing ........... .............. .............. .............. .............. .............. .............. ............. ............... 58 12. revision history ........................................................................................................... .................. 59
cs4954 cs4955 5 ds278f6 list of figures figure 1. video pixel data and control port timing ..................................................................8 figure 2. i2c host port timing ............................................................................................. ......9 figure 3. reset timing..................................................................................................... ........10 figure 4. itu r.bt601 input slave mode horizontal timing ...................................................16 figure 5. itu r.bt601 input master mode horizontal timing.................................................16 figure 6. vertical timing .................................................................................................. ........18 figure 7. ntsc video interlaced timing .................................................................................19 figure 8. pal video interlaced timing ....................................................................................20 figure 9. ntsc video non-interlaced prog ressive scan timing ............................................21 figure 10. pal video non-interlaced progre ssive scan timing .............................................22 figure 11. ccir656 input mode timing ..................................................................................22 figure 12. teletext timing (pulsation m ode) ...........................................................................25 figure 13. teletext timing (window mode) .............................................................................25 figure 14. 1.3 mhz chrominance low-pass filt er transfer characteristic..................................29 figure 15. 1.3 mhz chrominance low-pass f ilter transfer characterstic (passband) ...............29 figure 16. 650 khz chromina nce low-pass filter transfer characteristic ..................................29 figure 17. 650 khz chromina nce low-pass filter transfer char acteristic (passband) ...............29 figure 18. chrominance outp ut interpolation filter transfer ch aracteristic (passband).............30 figure 19. luminance interp olation filter transfer characteristic ..............................................30 figure 20. luminance interp olation filter transfer characterstic (passband) ............................30 figure 21. chrominance interpolation filter transfer characteristic for rgb datapath..............30 figure 22. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) ....31 figure 23. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) ....31 figure 24. chroma interp olator for rgb datapath when rgb_bw=0 -3 db ..............................31 figure 25. chroma interpol ator for rgb datapath when rgb_bw=0 (full scale).....................31 figure 26. i2c protocol.................................................................................................... .........35 figure 27. 8-bit parallel host port timing : read-write/write-read cycle...............................35 figure 28. 8-bit parallel host port timing : address read cycle .............................................36 figure 29. 8-bit parallel host port timing : address write cycle .............................................36 figure 30. external low pass filter ........................................................................................ .54 figure 31. typical connection diagram...... .............................................................................55
cs4954 cs4955 6 ds278f6 1. characteristics and specifications absolute maximum ratings ac & dc parametric specifications (agnd,dgnd = 0 v, all voltages with respect to 0 v ) warning: operating beyond these limits can result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd,dgnd = 0 v, all voltages with respect to 0 v.) note: operation outside the ranges is not recommended. thermal characteristics note: four-layer pcb recommended for operation in environments where ta > 70 c. dc characteristics (t a = 25 c; vaa, vdd = 5 v; gnda, gndd = 0 v.) parameter symbol min max units power supply vaa/vdd -0.3 6.0 v input current per pin (except supply pins) -10 10 ma output current per pin (except supply pins) -50 +50 ma analog input voltage -0.3 vaa + 0.3 v digital input voltage -0.3 vdd + 0.3 v ambient temperature power applied -55 + 125 c storage temperature -65 + 150 c parameter symbol min typ max units power supplies: digital analog vaa/vdd 3.15 4.75 3.3 5.0 3.45 5.25 v operating ambient temperature ta -40 +25 +85 c parameters symbol min typ max units allowable junction temperature - - 150 c junction to ambient thermal impedance - - - (four-layer pcb) tqfp ja-tm -45- c/w (two-layer pcb) tqfp ja-ts -65- parameter symbol min typ max units digital inputs high level input voltage v [7:0], pdat [7:0], hsync/vsync/clkin vih 2.2 - vdd+0.3 v high level input voltage i2c vih 0.7 vdd - - v low level input voltag e all inputs - -0.3 - 0.8 v input leakage current - -10 - +10 a digital outputs high level output voltage lo = -4 ma voh 2.4 - vdd v low level output voltage lo = 4 ma vol - - 0.4 v
cs4954 cs4955 ds278f6 7 notes: 1. values are by characterization only 2. output current levels with iset = 4 k , vref = 1.232 v. 3. dacs are set to low impedance mode 4. dacs are set to high impedance mode 5. times for black-to-white-level and white-to-black-level transitions. 6. low-z, 3 dacs on 7. high-z, 6 dacs on low level output voltage sda pin only, lo = 6ma vol - - 0.4 v output leakage current high-z digital outputs - -10 - +10 a analog outputs full scale output curren t cvbs/y/c/r/g/b (notes 1 , 2 , 3 ) io 32.9 34.7 36.5 ma full scale output curren t cvbs/y/c/r/g/b (notes 1 , 2 , 4 ) io 8.22 8.68 9.13 ma lsb current cvbs/y/c/r/g/b (notes 1 , 2 , 3 ) ib 32.2 33.9 35.7 a lsb current cvbs/y/c/r/g/b (notes 1 , 2 , 4 ) ib 8.04 8.48 8.92 a dac-to-dac matching (note 1 )mat - 2 4 % output compliance (note 1 )voc 0 - + 1.4 v output impedance (note 1 )rout - 15 - k output capacitance (note 1 )cout - - 30 pf dac output delay (note 1 )odel - 4 12 ns dac rise/fall time (note 1 , 5 )trf - 2.5 5 ns voltage reference reference voltage output vov 1.170 1.232 1.294 v reference input current (note 1 )uvc - - 10 a power supply supply voltage vaa, vdd 3.15 4.75 3.3 5.0 3.45 5.25 v digital supply current iaa1 - 70 150 ma analog supply low-z (note 6 ) iaa2 - 100 150 ma analog supply high-z (note 7 ) iaa3 - 60 100 ma power supply rejection ratio psrr 0.02 0.05 v / v static performance dac resolution (note 1 )--10bits differential non-linearity (note 1 ) dnl -1 + 0.5 + 1 lsb integral non-linearity (note 1 )inl - 2 + 1+ 2lsb dynamic performance differential gain (note 1 )dg - 2 5 % differential phase (note 1 )dp - + 0. 5 + 2 hue accuracy (note 1 )ha - - 2 signal to noise ratio snr 70 - - db saturation accuracy (note 1 )sat - 1 2 % parameter symbol min typ max units
cs4954 cs4955 8 ds278f6 ac characteristics parameter symbol min typ max units pixel input and control port (figure 1 ) clock pulse high time tch 14.82 18.52 22.58 ns clock pulse low time tcl 14.82 18.52 22.58 ns clock to data set-up time tisu 6 - - ns clock to data hold time tih 0 - - ns clock to data output delay toa - - 17 ns clk v[7:0] (inputs) hsync /vsync cb/field (1) /int (outputs) t ch t cl t isu t ih t oa figure 1. video pixel data and control port timing hsync /vsync
cs4954 cs4955 ds278f6 9 timing characteristics parameter symbol min typ max units i2c host port timing (figure 2 ) scl frequency fclk 1000 khz clock pulse high time tsph 0.1 s clock pulse low time tspl 0.7 s hold time (start cond.) tsh 100 ns setup time (start cond.) tssu 100 ns data setup time tsds 50 n s rise time tsr 1 s fall time tsf 0.3 s setup time (stop cond.) tss 100 ns bus free time tbuf 100 ns data hold time tdh 0 ns scl low to data out valid tvdo 600 ns figure 2. i2c host port timing sda scl t bu t sh t dh t ds t sh t ss t ssu t si t spi t sr t sph t vdo
cs4954 cs4955 10 ds278f6 timing characteristics (continued) parallel host port timing (figure 27 , 28 , 29 ) symbol min typ max units read cycle time trd 60 - - ns read pulse width trpw 30 - - ns address setup time tas 3 - - ns read address hold time trah 10 - - ns read data access time trda - - 40 ns read data hold time trdh 10 - 50 ns write recovery time twr 60 - - ns write pulse width twpw 40 - - ns write data setup time twds 8 - - ns write data hold time twdh 3 - - ns write-read/read-write recovery time trec 50 - - ns address from write hold time twac 0 - - ns reset timing (figure 3 ) reset pulse width tres 100 ns reset* t res figure 3. reset timing
cs4954 cs4955 ds278f6 11 2. additional cs4954/5 features ? five programmable dac output combinations, including yuv and second composite ? optional pseudo-progressive scan @ mpeg2 field rates ? stable color subcarri er for mpeg2 systems ? general purpose input and output pins ? individual dac power-down capability ? on-chip color bar generator ? supports rs170a and itu r.bt601 compos- ite output timing ? hsync and vsync ou tput in itu r.bt656 mode ? teletext encoding selectable on two composite and s-video signals ? programmable saturation, sch phase, hue, brightness and contrast ? device power-down capability ? super white and super black support 3. cs4954 introduction the cs4954/5 is a complete multi-standard digital video encoder implemented in current cmos tech- nology. the device can operate at 5 v as well as at 3.3 v. itu r.bt601- or itu r.bt656-compliant digital video input is converted into ntsc-m, ntsc-j, pal-b, pal-d, pal-g, pal-h, pal-i, pal-m, pal-n, or pal-n argentina-compatible analog video. the cs4954/5 is designed to con- nect, without glue logi c, to mpeg1 and mpeg2 digital video decoders. two 10-bit dac outputs provide high quality s- video analog output while another 10-bit dac si- multaneously generates composite analog video. in addition, there are three mo re dacs to provide si- multaneous analog rgb or analog yuv outputs. the cs4954/5 will accept 8-bit ycbcr or 8-bit yuv input data. the cs4954/5 is completely configured and con- trolled via an 8-bit host interface port or an i2c compatible serial interface. this host port provides access and control of all cs4954/5 options and fea- tures, such as closed ca ption insertion, interrupts, etc. in order to lower overa ll system costs, the cs4954/5 provides an inte rnal voltage reference that eliminates the requirement for an external, dis- crete, three-pin voltage reference. in iso mpeg-2 system configurations, the cs4954/5 can be augmente d with a common color- burst crystal to provide a stable color subcarrier given an unstable 27 mhz clock input. the use of the crystal is optional, but the facility to connect one is provided for mp eg-2 environments in which the system clock fre quency variability is too wide for accurate color sub-carrier generation. 4. functional description in the following subsecti ons, the functions of the cs4954/5 will be described. the descriptions refer to the device elements s hown in the block diagram on the cover page. 4.1 video timing generator all timing generation is accomplished via a 27 mhz input applied to the clk pin. the cs4954/5 can also accept a signal from an optional color burst crystal on the xtal_in & xtal_out pins. see the section, color subcarri- er synthesizer, for further details. the video timing generator is responsible for or- chestrating most of the ot her modules in the device. it operates in harmony wi th external sync input timing, or it can provide external sync timing out- puts. it automatically disa bles color burst on appro- priate scan lines and automatically generates serration and e qualization pulses on appropriate scan lines.
cs4954 cs4955 12 ds278f6 the cs4954/5 is designed to function as a video timing master or video timing slave. in both master and slave modes, all timi ng is sampled and assert- ed with the rising edge of the clk pin. in most cases, the cs4954/5 will serve as the video timing master. hsync , vsync , and field (1) are configured as outputs in master mode. hsync or field can also be defi ned as a composite blank- ing output signal in master mode. in master mode, the timing of hsync , vsync , field and com- posite blank (cb) signals is programmable. exact horizontal and vertical di splay timing is addressed in the operational description section. in slave mode, hsync and vsync are typically configured as input pins and are used to initialize independent vertical and horizontal timing genera- tors upon their respective falling edges. hsync and vsync timing must conf orm to the itu- r bt.601 specifications. the cs4954/5 also provides a itu r.bt656 slave mode in which the vide o input stream contains eav and sav codes. in this case, proper hsync and vsync timing is extracted automatically without any inputs other than the v [7:0]. itu r.bt656 input data that is sampled with the lead- ing edge of clk. in addition, it is also possible to output hsync and vsync signals when in itu r.bt656 slave mode. 4.2 video input formatter the video input formatte r translates ycbcr input data into yuv information, when necessary, and splits the luma and chroma information for filter- ing, scaling, and modulation. 4.3 color subcarrier synthesizer the subcarrier synthesize r is a digital frequency synthesizer that produces the appropriate subcarri- er frequency for ntsc or pal. the cs4954/5 generates the color burst frequency based on the clk input (27 mhz). color burst accuracy and stability are limited by th e accuracy of the 27 mhz input. if the frequency vari es, then the color burst frequency will also vary accordingly. for environments in whic h the clk input varies or jitters unacceptably, a local crystal frequency refer- ence can be used on the xtal_in and xtal_out pins. in this instance, the input clk is continuously compared with the external crystal ref- erence input and the internal timing of the cs4954/5 is automatically adjusted so that the color burst fre- quency remains within tolerance. controls are provided for phase adjustment of the burst to permit color ad justment and phase com- pensation. chroma hue control is provided by the cs4954/5 via a 10-bit hue control register (hue_lsb and h_msb). burst amplitude control is also made available to the host via the 8-bit burst amplitude register (sc_amp). 4.4 chroma path the video input formatte r delivers 4:2:2 yuv outputs to separate chroma and luma data paths. the chroma output of the video input formatter is directed to a chroma low-pass 19-tap fir filter. the filter bandwidth is selected (or the filter can be bypassed) via the control_1 register. the passband of the filter is either 650 khz or 1.3 mhz and the passband ripple is less than or equal to 0.05 db. the stopband for the 1.3 mhz selection begins at 3 mhz with an attenuation of greater than 35 db. the stopband for th e 650 khz selection be- gins around 1.1 mhz with an attenuation of greater than 20 db. the output of the chroma low-pass filter is connect- ed to the chroma interpol ation filter in which up- sampling from 4:2:2 to 4: 4:4 is accomplished. following the interpolat ion filter, the u and v chroma signals pass thro ugh two independent vari- note 1. the field pin (pin 9) re mains an output pin in slave mode. ho wever, the field pin state does not toggle in slave mode and its output state should be c onsidered random.
cs4954 cs4955 ds278f6 13 able gain amplifiers in which the chroma amplitude can be varied via the u_amp and v_amp 8-bit host addressable registers. the u and v chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. the chroma is then inter polated by a factor of two in order to operate the output dacs at twice the pixel rate. the interpolati on filters enable running the dacs at twice the pixe l rate which helps reduce the sinx/x roll-off for high er frequencies and reduc- es the complexity of th e external analog low pass filters. 4.5 luma path along with the chroma out put path, the cs4954/5 video input formatter has a parallel luma data out- put to a digital delay line. the delay line is a digital fifo. the fifo depth ma tches the clock period delay associated with the more complex chroma path. brightness adjustment is also provided via the 8-bit brightness_offset register. following the luma delay, the data is passed through an interpolation filter that has a program- mable bandwidth, followed by a variable gain am- plifier. the amplifier dc luma gain can be changed using the the y_amp register. the output of the luma amplifier connects to the sync insertion block. sy nc insertion is accom- plished by multiplexing, into the luma data path, the different sync dc values at the appropriate times. the digital sync generator takes horizontal sync and vertical sync ti ming signals and generates the appropriate composit e sync timing (including vertical equalization and serration pulses), blank- ing information, a nd burst flag. the sync edge rates conform to rs-170a or itu r.bt601 and itu r.bt470 specifications. it is also possible to delay the luminance signal, with respect to the ch rominance signal, by up to three pixel clocks. this va riable delay is useful to offset different propaga tion delays of the luma baseband and modulated ch roma signals. this ad- justable luma delay is available only on the cvbs_1 output. 4.6 rgb path and component yuv path the rgb datapath has the same latency as the luma and chroma path. therefore all six simultaneous analog outputs are synchr onized. the 4:2:2 ycbcr data is first interpolated to 4:4:4 and then interpo- lated to 27 mhz. the colo r space conversion is per- formed at 27 mhz. the coefficients for the color space conversion conform to the itu r.bt601 specifications. after color space conversi on, the amplitude of each component can be independently adjusted via the r_amp, g_amp, and b_amp 8-bit host address- able registers. a synchr onization signal can be add- ed to either one, two or all of the rgb signals. the synchronization signal conforms to ntsc or pal specifications. some applications (e.g ., projection tvs) require analog component yuv signa ls. the chip provides a programmable mode that outputs component yuv data. sync can be added to the luminance sig- nal. independent gain adjustment of the three com- ponents is provided as well. 4.7 digital to analog converters the cs4954/5 provides six discrete 27 mhz dacs for analog video. the defa ult configuration is one 10-bit dac for s-video ch rominance, one 10-bit dac for s-video luminan ce, one 10-bit dac for composite output, and three 10-bit dacs for rgb outputs. all six dacs are designed for driving ei- ther low-impedance loads (double terminated 75 ) or high-impedance lo ads (double terminated 300 ). there are five di fferent dac configura- tions to choose from (see table 1 , below). the dacs can be put in to high-impedance mode via host-addressable contro l register bits. each of
cs4954 cs4955 14 ds278f6 the six dacs has its own associated dac enable bit. in the disable mode, the 10-bit dacs source (or sink) zero current. when running the dacs with a low-impedance load, a minimum of three dacs must be powered down. when running the dacs with a high-imped- ance load, all the dacs can be enabled simulta- neously. for lower power standby s cenarios, the cs4954/5 also provides power shut-o ff control for the dacs. each dac has an associated dac shut-off bit. 4.8 voltage reference the cs4954/5 is equipped with an on-board volt- age reference generator (1.232 v) that is used by the dacs. the internal reference voltage is accu- rate enough to guarantee a maximum of 3% overall gain error on the anal og outputs. however, it is possible to override the in ternal reference voltage by applying an external vol tage source to the vref pin. 4.9 current reference the dac output current-pe r-bit is derived in the current reference block. th e current step is speci- fied by the size of resist or placed between the iset current reference pin and electrical ground. a 4 k resistor needs to be connected between iset pin and gnda. the dac output currents are optimized to drive either a doubly terminated 75 w load (low impedence m ode) or a double terminated 300 load (high impedence mode). the 2 output current modes are software selectable via a register bit. 4.10 host interface the cs4954/5 provides a para llel 8-bit data inter- face for overall configura tion and control. the host interface uses active-low read and write strobes, along with an active-low address enable signal, to provide microprocessor-comp atible read and write cycles. indirect host addr essing to the cs4954/5 in- ternal registers is accomp lished via an internal ad- dress register that is uniquely accessible via bus write cycles for the device when the host address enable signal is asserted. the cs4954/5 also provides an i2c-compatible se- rial interface for device configuration and control. this port can operate in st andard (up to 100 kb/sec) or fast (up to 400 kb/sec) modes. when in i2c mode, the parallel data interface pins, pdat [7:0], can be used as a genera l purpose i/o port controlled by the i2c interface. 4.11 closed caption services the cs4954/5 supports the generation of ntsc closed caption services. line 21 and line 284 cap- tioning can be generated and enabled independent- ly via a set of control registers. when enabled, clock run-in, start bit, a nd data bytes are automati- cally inserted at the appr opriate video lines. a con- venient interrupt protocol simplifies the software interface between the host processor and the cs4954/5. dac pin # mode 1 mode 2 mode 3 mode 4 mode 5 y 48 y y y cvbs_2 cvbs_2 c47ccc - - cvbs 44 cvbs_1 cvbs_1 cvbs_1 cvbs_1 cvbs_1 r 39 r cr (v) - r cr (v) g 40 g y cvbs_2 g y b43bcb (u)- bcb (u) table 1. dac configuration modes
cs4954 cs4955 ds278f6 15 4.12 teletext services the cs4954/5 encodes the most common teletext formats, such as european teletext, world stan- dard teletext (pal and ntsc), and north ameri- can teletext (nabts). teletext data can be inserted in any of the tv lines (blanking lines as well as active lines). in addition the blanking lines can be individually allocated for teletext instantiation. the input timing for teletext data is user program- mable. see the section teletext services for further details. teletext data can be inde pendently inserted on ei- ther one or all of the cvbs_1, cvbs_2, or s-video signals. 4.13 wide-screen signaling support and cgms insertion of wide-scree n signal encoding for pal and ntsc standards is supported and cgms (copy generation management system) for ntsc in japan. wide-screen signals are inserted in lines 23 and 336 for pal, and lines 20 and 283 for ntsc. 4.14 vbi encoding this chip supports the tr ansmission of control sig- nals in the verti cal blanking time in terval according to smpte rp 188 recomm endations. vbi encoded data can be independently in serted into any or all of cvbs_1, cvbs_2 or s-video signals. 4.15 control registers the control and configuration of the cs4954/5 is accomplished primarily through the control regis- ter block. all of the cont rol registers are uniquely addressable via the internal address register. the control register bits ar e initialized during device reset. see the programming section of this data sheet for the individual register bit allocations, bit operation- al descriptions, and initialization states. 4.16 testability the digital circuits are completely scanned by an internal scan chain, t hus providing close to 100% fault coverage. 5. operational description 5.1 reset hierarchy the cs4954/5 is equipped wi th an active low asyn- chronous reset input pin, reset . reset is used to initialize the internal regist ers and the internal state machines for subsequent default operation. see the electrical and timing specif ication section of this data sheet for specifi c cs4954/5 device reset and power-on signal timi ng requirements and re- strictions. while the reset pin is held low, the host interface in the cs4954/5 is disabled and will not respond to host-initiated bus cycles. all outputs are valid after a time period following reset pin low. a device reset initializ es the cs4954/5 internal registers to their default values as described by ta- ble 9 , control registers. in the default state, the cs4954/5 video dacs are di sabled and the device is internally configured to provide blue field video data to the dacs (any input data present on the v [7:0] pins is ignored at this time). otherwise, the cs4954/5 registers are configured for ntsc-m output and itu r.bt601 output timing operation. at a minimum, the dac registers (0x04 and 0x05) must be written (to enable the dacs) and the in_mode bit of the control_0 register (0x01) must be set (to en able itu r.bt601 data in- put on v [7:0]) for the cs 4954/5 to become opera- tional after reset.
cs4954 cs4955 16 ds278f6 5.2 video timing 5.2.1 slave mode input interface in slave itu r.bt601 (not itu-r.bt656 input) mode, the cs4954/5 receives signals on vsync and hsync as inputs. slave mode is the default following reset and is changed to master mode via a control register bit (control_0 [4]). the cs4954/5 is limited to itu r.bt601 horizontal and vertical input timing. all clocking in the cs4954/5 is generated from the clk pin. in slave mode, the sync generator uses externally provided horizontal and vertical sync signals to synchronize the internal timing of the cs4954/5. video data that is sent to the cs4954/5 mu st be synchronized to the horizontal and vertical sync signals. figure 4 illus- trates horizontal timing for itu r.bt601 input in slave mode. note that the cs4954/5 expects to re- ceive the first active pixel data on clock cycle 245 (ntsc) when control_2 register (0x02) bit sync_dly = 0. when s ync_dly = 1, it expects the first active pixel data on clock cycle 246 (ntsc). 5.2.2 master mode input interface the cs4954/5 defaults to slave mode following reset high but can be switch ed into master mode via the mstr bit in the control_0 register (0x00). in master mode , the cs4954/5 uses the vsync , hsync and field device pins as out- puts to schedule the proper external delivery of dig- ital video into the v [7:0] pins. figure 5 illustrates horizontal timing for the ccir601 input in master mode. the timing of the hsync output is selectable in the prog_hs register s (0x0d, 0x0e). hsync can be delayed by one full line cycle. the timing of the vsync output is also selectable in the clk 1706 active pixel #720 hsync (input) v[7:0] (sync_dly=0) 1705 1704 1703 1728 1 23 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 23 128 129 244 245 246 247 248 y cr y cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count 1702 1682 active pixel #720 v[7:0] (sync_dly=1) y cr y cb y cr horizontal blanking active pixel #1 active pixel #2 cb active pixel #719 figure 4. itu r.bt601 input slave mode horizontal timing clk 1706 active pixel #720 hsync (output) v[7:0] 1705 1704 1703 1728 1 23 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 23 128 129 244 245 246 247 248 y cr y cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count cb (output) 1702 1682 figure 5. itu r.bt601 input master mode horizontal timing
cs4954 cs4955 ds278f6 17 prog_vs register (0x0d). vsync can be de- layed by thirteen lines or advanced by eighteen lines. 5.2.3 vertical timing the cs4954/5 can be configured to operate in any of four different timing modes: pal, which is 625 vertical lines, 25 frames per second interlaced; ntsc, which is 525 vertical lines, 30 frames per second interlaced; and eith er 625 or 525 line pseu- do-progressive scan (see ?progressive scan? on page 18 ) . these modes are selected in the control_0 register (0x00). the cs4954/5 conforms to standard digital decom- pression dimensions and do es not process digital input data for the active analog video half lines as they are typically in the over/underscan region of tv display. 240 active line s total per field are pro- cessed for ntsc, and 288 active lines total per field are processed for pa l. frame vertical dimen- sions are 480 lines for ntsc and 576 lines for pal. table 2 specifies active lin e numbers for both ntsc and pal. refer to figure 6 for hsync , vsync and field signal timing. 5.2.4 horizontal timing hsync is used to synchr onize the horizontal-in- put-to-output timing in orde r to provide proper hor- izontal alignment. hsync defaults to an input pin following reset but switches to an output in mas- ter mode (control_0 [4] = 1). horizontal tim- ing is referenced to hsync transitioning low. for active video lines, digital video input is to be ap- plied to the v [7:0] input s for 244 (ntsc) or for 264 (pal) clk periods fo llowing the leading (falling) edge of hsync if the prog_hs regis- ters are set to default values. 5.2.5 ntsc interlaced the cs4954/5 supports ntsc-m, ntsc-j and pal-m modes where there are 525 total lines per frame, two fixed 262.5-line fields per frame and 30 frames occurring per sec ond. ntsc interlaced ver- tical timing is illustrated in figure 7 . each field consists of one line fo r closed caption, 240 active lines of video, plus 21.5 lines of blanking. vsync field one transitions low at the beginning of line four and will re main low for three lines or 2574 pixel cycles (858 3). the cs4954/5 exclu- sively reserves line 21 of field one for closed cap- tion insertion. digital video input is expected to be delivered to the cs4954/5 v [7:0] pins for 240 lines beginning on active video lines 22 and con- tinuing through line 261. vsync field two transi- tions low in the middle of line 266 and stays low for three line-times and tran sitions high in the middle of line 269. the cs4954/5 ex clusively reserves line 284 of field two for closed caption insertion. video input on the v [7:0] pins is expected between lines 285 through line 525. 5.2.6 pal interlaced the cs4954/5 supports pal modes b, d, g, h, i, n, and combination n, in which there are 625 total lines per frame, two fi xed 312.5 line fields per frame, and 25 total fr ames per second. figure 8 il- lustrates pal interlaced ve rtical timing. each field consists of 287 active line s of video plus 25.5 lines of blanking. vsync will transition low to begin field one and will remain low for 2.5 li nes or 2160 pixel cycles (864 2.5). digital video i nput is expected to be delivered to the cs4954/5 v [7:0] pins for 287 lines beginning on active vi deo line 24 and continu- ing through line 310. field two begins with vsync transitioning low after 312.5 lines from the beginning of field one. mode field active lines ntsc 1, 3; 2, 4 22-261; 285-524 pal 1, 3, 5, 7; 2, 4, 6, 8 23-310; 336-623 ntsc progressive-scan na 22-261 pal progressive-scan na 23-310 table 2. ve r t i c a l ti m i n g
cs4954 cs4955 18 ds278f6 vsync stays low for 2.5 line -times and transitions high with the beginning of line 315. video input on the v [7:0] pins is e xpected between line 336 through line 622. 5.2.7 progressive scan the cs4954/5 supports a pseudo-progessive scan mode for which ?odd? a nd ?even? numbered line information is presented in ?odd? numbered line positions by varying the ve rtical blanking timing. this preserves precise mpeg-2 frame rates of 30 and 25 frames pe r second. this mode is in contrast to other digital video encoders, which commonly support progressive scan by repetitively displaying a 262 line field (524/525 lines for ntsc). the common method is flawed: over time, the output display rate will overr un a system-clock-locked mpeg-2 decompressor and display a field twice every 8.75 seconds. 5.2.8 ntsc progressive scan vsync will transition low at line four to begin field one and will remain low for three lines or 2574 pixel cycles (858 3) . ntsc interlaced tim- ing is illustrated in figure 9 . in this mode, the cs4954/5 expects digital vide o input at the v [7:0] pins for 240 lines beginni ng on active video line 22 and continuing through line 261. ntsc vertical timing (odd field) line hsync vsync field 3 4 5 6 7 8 9 10 ntsc vertical timing (even field) pal vertical timing (odd field) pal vertical timing (even field) 264 265 266 267 268 269 270 271 265 1 2 3 4 5 6 7 311 312 313 314 315 316 317 318 line hsync vsync field line hsync vsync field line hsync vsync field figure 6. vertical timing
cs4954 cs4955 ds278f6 19 field two begins with vsync transitioning low at line 266. vsync stays low for 3 line cycles and transitions high during th e end of line 268. video input on the v [7:0] pins is expected between line 284 and line 522. field two is 263 lines; field one is 262 lines. 5.2.9 pal progressive scan vsync will transition low at the beginning of the odd field and will remain low for 2.5 lines or 2160 pixel cycles (864 2.5). pal non-interlaced tim- ing is illustrated in figure 10 . in this mode, the cs4954/5 expects digital video input on the v [7:0] pins for 288 lines, beginni ng on active video line 23 and continuing through line 309. the second field begins with vsync transitioning low after 312 lines from th e beginning of the first field. vsync stays low for 2.5 li ne-times and tran- sitions high during the mi ddle of line 315. video input on the v [7:0] pins is expected between line 335 through line 622. field two is 313 lines; field one is 312 lines. 5.3 itu-r.bt656 the cs4954/5 supports an itu-r.bt656 slave mode feature that is selectable through the itu- r.bt656 bit of the cont rol_0 register. the itu-r.bt656 slave feature is unique because the horizontal and vertical ti ming and digital video are combined into a single 8-bit 27 mhz input. with itu-r.bt656 there are no horizontal and vertical input or output strobes, only 8-bit 27 mhz active cbycry data, with start- and end-of-video codes implemented using reserved 00 and ff code se- quences within the video feed. as with all modes, v [7:0] are sampled with the rising edge of clk. the cs4954/5 expects the digital itu-r.bt656 stream to be error-free. the field (1) output tog- gles as with non it u-r.bt656 input. itu- r.bt656 input timing is illustrated in figure 11 . 523 524 525 1 2 3 4 5 6 7 8 9 vsync drops 10 22 analog field 1 261 262 263 analog field 2 285 284 272 271 270 269 268 267 266 265 264 523 524 525 123456789 vsync drops 10 22 analog field 3 261 262 263 analog field 4 285 284 272 271 270 269 268 267 266 265 264 burst begins with positive half-cycle burst begins with negative half-cycle figure 7. ntsc video in terlaced timing
cs4954 cs4955 20 ds278f6 as mentioned above, there are no horizontal and vertical timing signals necessary in itu-r.bt656 mode. however in some cases it is advantageous to output these timing signals for other purposes. by setting the 656_sync_out register bit in control_6 register, hsync and vsync are output,so that other device s in the system can syn- chronize to these timing signals. 621 622 623 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 2 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 3 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 4 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 5 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 6 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 7 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 8 308 311 312 313 314 315 316 317 318 319 320 336 337 vsync drops figure 8. pal video interlaced timing
cs4954 cs4955 ds278f6 21 5.4 digital video input modes the cs4954/5 provides two different digital video input modes that are selectable through the in_mode bit in the control_0 register. in mode 0 and upon re set, the cs4954/5 de- faults to output a solid co lor (one of a possible of 256 colors). the backgro und color is selected by writing the bkg_color register (0x08). the colorspace of the register is rgb 3:3:2 and is unaf- fected by gamma correction. the default color fol- lowing reset is blue. in mode 1 the cs4954/5 s upports a single 8-bit 27 mhz cbycry source as input on the v [7:0] pins. input video timing can be itu-r.bt601 mas- ter or slave or itu-r.bt656. 5.5 multi-standard output format modes the cs4954/5 supports a wide range of output for- mats compatible with wo rldwide broadcast stan- dards. these formats include ntsc-m, ntsc-j, pal-b/d/g/h/i, pal-m, pal-n, and pal com- bination n (pal-nc) which is the broadcast stan- dard used in argentina. after reset, the cs4954/5 defaults to ntsc-m operation with itu-r.bt601 analog timing. ntsc-j can also be supported in the japanese format by turn ing off the 7.5 ire pedestal through the ped bit in the control_1 register (0x01). output formats are conf igured by writing control registers with the values shown in table 3 . 261 262 123456789 start of vsync 10 22 field 1 burst begins with positive half-cycle burst begins with negative half-cycle burst phase = reference phase = 180 relative to b-y 0 burst phase = reference phase = 180 relative to b-y 0 262 263 12345678910 22 261 262 12345678910 22 262 263 12345678910 22 field 2 field 3 field 4 start of vsync figure 9. ntsc video non-interlaced progressive scan timing note 1: the field pin (pin 9) rema ins an output pin in slave mode. ho wever, the field pi n state does not toggle in slave mode and its ou tput state should be considered random.
cs4954 cs4955 22 ds278f6 5.6 subcarrier generation the cs4954/5 automatica lly synthesizes ntsc and pal color subcarrier clocks using the clk fre- quency and four control registers (sc_synth0/1/2/3). the ntsc subcarrier syn- thesizer is reset every four fields (every eight fields for pal). the sc_synth0/1/2/3 registers used together provide a 32-bit value that defaults to ntsc (43e0f83eh) following reset. table 4 shows the 32-bit value required fo r each of the different broadcast formats. 309 310 311 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 312 313 1 2 3 4 5 6 7 23 24 309 analog field 2 308 311 312 vsync drops 12345 6 7 23 24 310 309 310 311 analog field 3 312 313 1 2 3 4 5 6 7 23 24 309 analog field 4 308 311 312 12345 6 7 23 24 310 figure 10. pal video non-interlaced progressive scan timing y cr y ff 00 00 xy 80 10 80 10 80 10 80 10 80 10 80 10 80 10 ff 00 00 xy cb y cr cb y cr 1440 clocks active video sav code composite video ancilliary data 268 clocks (ntsc) 280 clocks (pal) horizontal blanking eav code 4 clocks active video v[7:0] itu r.bt656 4 clocks figure 11. ccir656 input mode timing data
cs4954 cs4955 ds278f6 23 5.7 subcarrier compensation since the subcarrier is s ynthesized from clk, the subcarrier frequency error will track the clock fre- quency error. if the input clock has a tolerance of 200 ppm then the resultin g subcarrier will also have a tolerance of 200 ppm. per the ntsc speci- fication, the final subcarrier tolerance is 10 hz which is approximately 3 p pm. care must be taken in selecting a suitable clock source. in mpeg-2 system envir onments the clock is actu- ally recovered from the da ta stream. in these cases the recovered clock can be 27 mhz 50 ppm or 1350 hz. it varies per television, but in many cas- es given an mpeg-2 sy stem clock of 27 mhz, 1350 hz, the resu ltant color subcarrier produced will be outside of the te levision?s ability to com- pensate and the chromina nce information will not be displayed (resulting in a black-and-wh ite picture only). the cs4954/5 is designed to provide automatic compensation for an excessively inaccurate mpeg-2 system clock. s ub-carrier compensation is enabled through the xtal bit of the control_2 register. when enabled, the cs4954/5 will utilize a co mmon quartz color burst crystal (3.579545 mhz 50 ppm for ntsc) at- tached to the xtal_in and xtal_out pins to automatically compare and compensate the color subcarrier synthesis process. 5.8 closed caption insertion the cs4954/5 is capable of ntsc closed caption insertion on lines 21 and 284 independently. closed captioning is enable d for either one or both lines via the cc_en [1:0] register bits and the data to be inserted is also written into the four closed caption data registers. the cs4954/5, when enabled, automatically generates the seven cycles of clock run-in ( 32 times the line rate), does start bit insertion (001), and finally does insertion of the two data byt es per line. data low at the video outputs corresponds to 0 ir e and data high corre- sponds to 50 ire. there are two independent 8-bit registers per line (cc_21_1 & cc_21_2 for line 21 and cc_284_1 & cc_284_2 for line 284). in terrupts are also pro- vided to simplify the ha ndshake between the driver software and the device. typically the host writes system fsubcarrier value (hex) ntsc-m, ntsc-j 3.5795455 mhz 43e0f83e pal-b, d, g, h, i, n 4.43361875 mhz 54131596 pal-n (argentina) 3.582056 mhz 43ed288d pal-m 3.579611 mhz 43cddfc7 table 3. address register ntsc-m itu r.bt601 ntsc-j itu r.bt601 ntsc-m rs170a pal- b,d,g,h,i pal-m pal-n pal-n comb. (argent) 000 control_0 01h 01h 21h 41h 61h a1h 81h 001 control_1 12h 10h 16h 30h 12h 30h 30h 004 control_4 07h 07h 07h 07h 07h 07h 07h 005 control_5 78h 78h 78h 78h 78h 78h 78h 010 sc_amp 1ch 1ch 1ch 15h 15h 15h 15h 011 sc_synth0 3eh 3eh 3eh 96h c7h 96h 8ch 012 sc_synth1 f8h f8h f8h 15h dfh 15h 28h 013 sc_synth2 e0h e0h e0h 13h cdh 13h edh 014 sc_synth3 43h 43h 43h 54h 43h 54h 43h table 4. multi-standard format register configurations
cs4954 cs4955 24 ds278f6 all 4 bytes to be inserted to the registers and then enables closed caption inse rtion and interrupts. as the closed caption interrupts occur, the host soft- ware responds by writing the next two bytes to be inserted to the correct control registers and then clears the interrupt and wa its for the next field. 5.9 programmable h-sync and v-sync it is possible in master mode to change the h-sync and v-sync times based on register settings. pro- grammable h-sync and v-s ync timing is helpful in systems where control signal latencies are present. the user can then program h-sync and v-sync tim- ing according to their syst em requirements. the de- fault values are 244, and 264 for ntsc and pal respectively. h-sync can be delayed by a full line, in 74 nsec in- tervals. v-sync can be shifted in time in both directions . the default values are 18 and 23 for ntsc and pal respectively. since the v-sync register is 5 bits wide (sync register 0), the v-sync pulse can be shifted by 31 lines total. v-sync timing can preceed its default timing by a maximum of 18 lines (ntsc) or 23 lines (pal) and can be delayed from its default timing by a maximum of 13 lines (ntsc) or 8 lines (pal). 5.10 wide screen signaling (wss) and cgms wide screen signaling su pport is provided for ntsc and for pal standard s. wide screen signal- ing is currently used in most countries with 625 line systems as well as in japan for edtv-ii applica- tions. for a complete desc ription of the wss stan- dard, please refer to itu-r bt.1119 (625 line system) and to eiaj cpx1204 for the japanese 525 line system standard. the wide screen signal is transferred in a blanking line of each video fiel d (ntsc: lines 20 and 283, pal: lines 23 and 336). wi de screen signaling is enabled by setting ww_23 to ?1?. some countries with pal standard don?t use line 336 for wide screen signaling (they use only line 23), therefore we provide another enab le bit (wss_22) for that particular line. there are 3 registers dedicated to contain the trans- mitted wss bits (w ss_reg_0, wss_reg_1, wss_reg_2). the data insertion into the appro- priate lines is performed automatically by this de- vice. the run-in and start code bits do not have to be loaded into this device. it automatically inserts the correct code at th e beginning of transfer. 5.11 teletext support this chip supports severa l teletext standards in- cluding european teletext , nabts (north ameri- can teletext), and wst (w orld standard teletext) for ntsc and pal. all of these teletext stan dards are defined in the itu-r bt.653-2 document. the european tele- text is defined as ? teletext system b ? for 625/50 hz tv systems. nabts teletext is defined as ? teletext system c ? for 525/60 hz tv systems. wst for pal is defined as ? teletext system d ? for 624/50 hz tv systems and wst for ntsc is defined as ? teletext system d ? for 525/60 hz tv systems. this chip provides indepe ndant teletext encoding into composite 1, composit e 2 and s-video signals. the teletext encoding into these various signals is software programmable. in teletext pulsation mode, (ttx_window=0), register 031 bit 3, the pin ttxdat receives a teletext bitstream sample d at the 27 mhz clock. at each rising edge of the ttxrq output signal a sin- gle teletext bit has to be provided after a program- mable input delay at the ttxdat input pin. phase variant interpolation of the data in the inter- nal teletext encoder result s in minimal phase jitter on the ouput text lines.
cs4954 cs4955 ds278f6 25 ttxrq provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at independently selectable lines for both tv fields. th e internal insertion win- dow for text is set to ei ther 360, 296 or 288 teletext bits, depending on the selected teletext standard. the clock run-in is included in this window. teletext in enabled by setting the ttx_en bit to ?1?. the ttx_wst bit in conjunction with the tv_format register select s one of the 4 teletext encoding possibilities. the teletext timing is shown in the figure 12 . ttxhs and ttxhd are user programmable and therefore allow the user to have full control over when teletext data is sent to this device. the time t fd is the time needed to interpolate tele- text input data and insert it into the cvbs and y output signals, such th at it appears between t ttx = 9.8 s and t ttx =12 s after the leading edge of the horizontal synchronization pulse. t fd changes with the tv st andard and the selected teletext standard. please refer to itu-r bt.653-2 for more detailed information. the time t pd is the pipeline delay time introduced by the source that is ga ted by ttxrq in order to deliver teletext data. th is delay is programmable through the register ttxhd. for every active high transition at output pin ttxrq, a new tele- text bit must be provide d by the source. the time between the beginning of the first ttxrq pulse and the leading edge of h-sync is programmable through the ttxhs register. since the beginning of th e pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable, the ttxdat data is always inserted at the correct position after the leading edge of the outgoing hor izontal synchronization pulse. the time t ttxwin is the internally used insertion window for ttx data; it has a constant length depending on the selected te letext standard which allows insertion of 360 ttx bits (6.9375 mbit/sec) (european te letext) or 296 ttx bits (5.6427875 mbit/sec) (wst pa l) or 288 ttx bits (5.727272 mbit/sec) (nabts) or 296 ttx bits (5.727272 mbit/sec) (wst ntsc) respectively. using the appropriate programming, all suitable lines of the odd fiel d (ttxovs through ttx- ove) plus all suitable li nes of the even field (ttxevs through ttxeve) can be used for tele- text insertion. in addition it is possible to selec- tively disable the teletext insertion on single lines. this can be programmed by setting the ttx_line_dis1, ttx_line_dis2 and ttx_line_dis3 registers appropriately. note that the ttxdat si gnal must be synchro- nized with the 27 mhz clock. the pulse width of the ttxrq signal varies between three and four 27 mhz clock cycles. the va riation is necessary in figure 12. teletext timing (pulsation mode) figure 13. teletext timing (window mode) cvbs/y ttxrq ttxdat textbit #: 1 2 3 4 5 t ttx t ttxwin t pd t fd cvbs/y ttxrq ttxdat textbit #:12345 t ttx t ttxwin t pd t fd
cs4954 cs4955 26 ds278f6 order to maintain the strict timing requirements of the teletext standard. table 5 shows how to program the ttxhs register for teletext instantiation into the analog signals for the various supported tv formats. ttxhs is the time between the leading edge of the hsync sig- nal and the rising edge of the first ttxrq signal and consists of multiples of 27 mhz clock cycles note that with increasi ng values of ttxhs the time t ttx increases as well. the time t fd accounts for the internal pipeline delay due to processing, synchronization and instan tiation of the teletext data. the time t pd is dependant on the ttxhd register. note that the teletext data bits are shaped according to the itu r.bt653-2 specifications. if register 031 bit 3 is set, (ttx_window=1) the teletext is in window s mode. in this mode, the request pulses become a window where the bit pro- vided on the ttxdat pin is valid (see figure 13 ). in pulse mode (where th e number of request pulses are determined by the telete xt standard chosen), the length of the window must be programmed by the user independent of the te letext standard used. the length of the window is programmed through reg- ister 029 ttxhs (start of window), register 02a (ttxhd) and regi ster 031 (end of win- dow). the end-of-window re gister is a 11 bit value. in teletext window mode, the ttxhs value can be selected using the values in table 5 . although these values may need to be adjusted to match your system delay, use the fo llowing equation to com- pute the ttxhd value: ttxhs + 1402 = ttxhd (for europe) ttxhs + 1151 = ttxhd (for wst) ttxhs + 1122 = ttxhd (for nabts) 5.12 color bar generator the cs4954/5 is e quipped with a color bar genera- tor that is enabled through the cbar bit of the control_1 register. th e color bar generator works in master or slave mode and has no effect on the video input/output timing. if the cs4954/5 is configured for slave mode color bars, proper video timing must be present on the hsync and vsync pins for the color bars to be displayed. given proper slave mode input timing or master mode timing, the color bar generator will override the video input pixel data. the output of the color bar generator is instantiated after the chroma interpolat ion filter and before the luma delay line . the generated color bar numbers are for 100% amplitude , 100% saturation ntsc eia color bars or 100% amplitude, 100% satura- tion pal ebu color bars. for pal color bars, the cs4954/5 generates ntsc color bar values, which are very close to standa rd pal values. the exact luma and chroma values are listed in table 6 . tv standard teletext standard ttxhs (register value) t ttx ntsc-m nabts 161 10.5 s ntsc-m wst-ntsc 142 9.8 s pal-b europe ttx 204 12.0 s pal-b wst-pal 163 10.5 s pal-m nabts 161 10.5 s pal-m wst-ntsc 142 9.8 s pal-n (non arg.) europe ttx 204 12.0 s pal-n (non arg.) wst-pal 163 10.5 s pal-n (arg.) europe ttx 204 12.0 s pal-n (arg.) wst-pal 163 10.5 s table 5. teletext timing parameters
cs4954 cs4955 ds278f6 27 5.13 vbi encoding vbi (vertical blanking in terval) encoding is per- formed according to smpte rp 188 recommenda- tions. in ntsc mode, li nes 10 - 20 and lines 272 - 283 are used for the transmi ssion of ancillary data. in pal mode lines 6 - 22 and lines 318 -335 are used. the vbi encoding m ode can be set through the control_3 register. all digital input data is passed through the chip when this mode is enable d. it is therefore the re- sponsibility of the user to ensure appropriate ampli- tude levels. table 7 shows the relationship of the digital input signal and the analog output voltage. each lsb corresponds to a step of 5 mv in the out- put voltage. 5.14 super white/super black support the itu-r bt.601 recomme ndation limits the al- lowed range for the digital video data between 010 - 0eb for luma and between 010 - 0f0 for the chrominance values. this chip will clip any digital input value which is out of this range to con- form to the itu-r bt.601 specifications. however for some applications it is useful to allow a wider input range. by se tting the clip_off bit (control_6 register), the allowed input range is extended to 001 - 0fe for both luma and chromi- nance values. note that 000 and 0ff values are never allowed, since they are reserved for synchronization infor- mation. 5.15 interrupts in order to better su pport precise video mode switches and to establish a software/hardware handshake with the closed caption insertion block, the cs4954/5 is equipped with an interrupt pin named int. the int pin is active high. there are three interrupt sources: vsync , line 21, and line 284. each interrupt can be individually disabled with the int_en register . each interrupt is also cleared via writing a one to the corresponding int_clr register bits. th e three individual inter- rupts are or-ed together to generate an interrupt signal which is presented on the int output pin. if an interrupt has occurre d, it cannot be eliminated with a disable, it must be cleared. 5.16 general purpose i/o port the cs4954/5 has a gpio por t and register that is available when the device is configured for i2c host interface operation. in i2c host interface mode, the pdat [7:0] pins are unused by the host interface and they can operate as i nput or output pins for the gpio_data_reg register (00a). the cs4954/5 also contains the gpio_ctrl_reg register (009) which is used to configure the gpio pins for input or output operation. the gpio port pdat [7:0] pins are configured for input operation when the corresponding gpio_ctrl_reg [7:0] bits are set to 0. in gpio input mode, the cs4954/5 will latch the data on the pdat [7:0] pins into the corresponding bit loca- color cb cr y white 0 0 + 167 yellow - 84 + 14 + 156 cyan + 28 - 84 + 138 green - 56 - 70 + 127 magenta + 56 + 70 + 110 red - 28 + 84 + 99 blue + 84 - 14 + 81 black 0 0 + 70 table 6. internal color bar values (8 -bit values, cb/cr are in twos complement format) digital input analog output voltage 0 38 286 mv 0 3b 300 mv 0 c4 1000 mv table 7. vbi encoding signal amplitudes
cs4954 cs4955 28 ds278f6 tions of gpio_data_reg when it detects regis- ter address 00a through the i2c interface. a detection of address 00a can happen in two ways. the first and most common way this will happen is when address 00a is written to the cs4954/5 via its i2c interface. the s econd method for detecting address 00a is implemented by accessing register address 009 through i2c. in i2c host interface op- eration, the cs4954/5 register address pointer will auto-increment to addres s 00a after an address 009 access. the gpio port pdat [7:0] pins are configured for output operation when the corresponding gpio_ctrl_reg [7:0] bits are set. in gpio out- put mode, the cs4954/5 wi ll output the data in gpio_data_reg [7:0] bit locations onto the corresponding pdat [7:0] pins when it detects a register address 00a through the i2c interface.
cs4954 cs4955 ds278f6 29 6. filter responses 0 1 2 3 4 5 6 x 10 6 -70 -60 -50 -40 -30 -20 -10 0 1.3 mhz. filter frequency response magnitude - db frequency (hz) figure 14. 1.3 mhz chrominance low-pass filter transfer characteristic figure 15. 1.3 mhz chrominance low- pass filter transfer characterstic (passband) 0 2 4 6 8 10 12 x 10 5 -0.5 -0.4 -0.3 -0.2 -0.1 0 1.3 mhz. filter passband response magnitude - db frequency (hz) 0 1 2 3 4 5 6 x 10 6 -30 -25 -20 -15 -10 -5 0 650 khz. filter frequency response magnitude - db figure 16. 650 khz chrominance low-pass filter transfer characteristic figure 17. 650 khz chrominance low-pass filter transfer characteristic (passband) 0 2 4 6 8 10 12 x 10 5 -3 -2.5 -2 -1.5 -1 -0.5 0 650 khz. filter passband response magnitude - db
cs4954 cs4955 30 ds278f6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 chroma output interpolator pass band frequency (mhz) magnitude response (db) figure 18. chrominance output interpolation filter transfer characteristic (passband) figure 19. luminance interpolation fi lter transfer charac- teristic 0 2 4 6 8 10 12 1 4 -40 -35 -30 -25 -20 -15 -10 -5 0 luma output interpolation filter response at 27mhz full scale frequency (mhz) magnitude response (db) 0 1 2 3 4 5 6 7 8 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 luma output interpolation filter response at 27 mhz (-3 db) frequency (mhz) magnitude response (db) figure 20. luminance interpolation filter transfer charac- terstic (passband) figure 21. chrominance interpolation filter transfer char- acteristic for rgb datapath 0 2 4 6 8 10 12 -40 -35 -30 -25 -20 -15 -10 -5 0 rgb datapath filter for rgb_bw = 0 full scale frequency (mhz) magnitude response (db)
cs4954 cs4955 ds278f6 31 0 2 4 6 8 10 12 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 rgb datapath filter when rgb_bw = 1 (reduced bandwidth) (-3 db) frequency (mhz) magnitude response (db) figure 22. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) figure 23. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) 0 2 4 6 8 10 12 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 rgb datapath filter when rgb_bw = 1 (reduced bandwidth) frequency (mhz) magnitude response (db) 0 2 4 6 8 10 12 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 rgb datapath filter for rgb_bw = 0 (-3 db) frequency (mhz) magnitude response (db) figure 24. chroma interpolator for rgb datapath when rgb_bw=0 -3 db figure 25. chroma interpolator for rgb datapath when rgb_bw=0 (full scale) 0 5 10 15 20 25 -40 -35 -30 -25 -20 -15 -10 -5 0 chroma output interpolator full scale frequency (mhz) magnitude response (db)
cs4954 cs4955 32 ds278f6 7. analog 7.1 analog timing all cs4954/5 analog timing a nd sequencing is de- rived from the 27 mhz clock input. the analog out- puts are controlled intern ally by the video timing generator in conjunction w ith master and slave tim- ing. since the cs4954/5 is almost entirely a digital cir- cuit, great care has been taken to guarantee analog timing and slew rate performance as specified in the ntsc and pal anal og specifications. refer- ence the analog parameters section of this data sheet for the performance specifications. 7.2 vref the cs4954/5 can operate wi th or without the aid of an external voltage reference. the cs4954/5 is designed with an internal voltage reference genera- tor that provides a vrefout signal at the vref pin. the internal voltage re ference is utilized by not making a connection to the vref pin. the vref pin can also be connected to an external precision 1.232 volt reference, which then overrides the in- ternal reference. 7.3 iset all six of the cs4954/5 di gital to analog converter dacs are output current normalized with a com- mon iset device pin. the dac output current per bit is determined by the size of the resistor connect- ed between iset and el ectrical ground. typically a 4k , 1% metal film resist or should be used. the iset resistance can be cha nged by the user to ac- commodate varying vide o output attenuation via post filters and also to suit individual preferred per- formance needs. in conjunction with the iset value, the user can also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that ar e used to control internal digital amplifiers. the dac output levels are de- fined by the following equations: vref/riset = iref (e.g., 1.232 v/4k = 308 a ) cvbs/y/c/r/g/b outputs in low impedance mode: vout (max) = iref*(16/145)*1023*37.5 = 1.304v cvbs/y/c/r/g/b outputs in high impedance mode: vout (max) = iref*(4/145)*1023*150 = 1.304 v 7.4 dacs the cs4954/5 is has six independent, video-grade, current-output, digital- to-analog converters (dacs). they are 10-bi t dacs operating at a 27 mhz two-times-oversam pling rate. all six dacs are disabled and de fault to low power mode upon reset. each dac can be individually pow- ered down and disabled. the output-current-per-bit of all six dacs is determined by the size of the re- sistor connected betwee n the iset pin and ground. 7.4.1 luminance dac the y output pin is driv en from a 10-bit 27 mhz current output dac that in ternally receives the y, or luminance (black and white only) or cvbs data based on its configuration. see table 1 and ?cvbs dac? on page 33 . the y dac is de- signed to drive proper video levels into a 37.5 load. reference the detail ed electrical section of this data sheet for the ex act y digital to analog ac and dc performance data. a en_l enable control bit in the control register 5 (005) is provided to enable or disable the luminance dac. to com- pletely disable or for low power device operation, the luminance dac can be totally shut down via the svidlum_pd control bit in control register 4 (004). in this mode, turn-on using the control register will not be instantaneous.
cs4954 cs4955 ds278f6 33 7.4.2 chrominance dac the c output pin is driven from a 10-bit 27 mhz current output dac that in ternally receives the c or chrominance portion of the video signal (color only). the c dac is designed to drive proper video levels into a 37.5 load. reference the detailed electrical section of this data shee t for the exact c digital to analog ac and dc performance data. the en_c enable control register bit in control register 1 (005) is provided to enable or disable the chrominance dac. to comp letely disable or for low power device operat ion, the chrominance dac can be totally shut down via the svidchr_pd register bit in control register 4 (004). in this mode turn-on using the control register will not be instantaneous. 7.4.3 cvbs dac the cvbs output pin is driven from a 10-bit 27 mhz current output dac that internally re- ceives a combined luma and chroma signal to pro- vide composite video output. the cvbs dac is designed to drive proper composite video levels into a 37.5 load. reference the detailed electrical section of this data sheet for the exact cvbs digital to analog ac and dc performance data. the en_com enable control re gister bit, in control register 1 (005), is provided to enable or disable the output pin. when disabled, there is no current flow from the output. to co mpletely disable or for low power device opera tion, the cvbs37 dac can be totally shut down vi a the comdac_pd control register bit in control register 4 (004). in this mode turn-on using the control register will not be instantaneous. 7.4.4 red dac the red output pin is driv en from a 10-bit 27 mhz current output dac that in ternally receives either red component video data or v (cr) data. the red dac is designed to drive proper component video levels into a 37.5 load. reference the detailed electrical section of this da ta sheet for the exact red digital to analog ac and dc performance data. the en_r enable control register bit in control regis- ter 1 (005) is provided to enable or disable the out- put pin. when disabled, there is no current flow from the output. to comple te disable or for low power device operation, the red dac can be totally shut down via the r_pd control register bit in control register 4 (004). in this mode turn-on using the control register will not be instantaneous. 7.4.5 green dac the green output pin is driven from a 10-bit 27 mhz current output dac that internally re- ceives either green com ponent video data, y lumi- nance data or cvbs data depending upon its configuration. see table 1 , ?cvbs dac? on page 33 and ?luminance dac? on page 32 . the green dac is designed to drive proper com- posite video levels into a 37.5 load. reference the detailed electrical secti on of this data sheet for the exact green digital to analog ac and dc perfor- mance data. the en_g enab le control register bit, in control register 1 (0 05), is provided to enable or disable the output pin. when disabled, there is no current flow from the output. to completely dis- able or for low power de vice operation, the green dac can be totally shut down via the g_pd con- trol register bit in control register 4 (004) . in this mode turn-on using the cont rol register will not be instantaneous. 7.4.6 blue dac the blue output pin is driven from a 10-bit 27 mhz current output dac that internally receives either blue component video data or u (cb) data. the blue dac is de signed to drive proper component video levels into a 37.5 load. reference the de- tailed electrical s ection of this data sheet for the ex- act blue digital to anal og ac and dc performance data. the en_b enable cont rol register bit, in con- trol register 5 (005), is provided to enable or dis- able the output pin. when disabled, there is no
cs4954 cs4955 34 ds278f6 current flow from the out put. to completely dis- able or for low power device operation, the blue dac can be totally shut down via the b_pd con- trol register bit in cont rol register 4 (004). in this mode turn-on using the control register will not be instantaneous. 7.4.7 dac useage rules if some of the 6 dacs ar e not used, it is strongly recommended to pow er them down (see control_4 register) in order to reduce the pow- er dissipation. depending on the external re sistor connected to the iset pin the output drive of the dacs can be changed. an external resistor of 4 k must be con- nected to the iset pin for normal operation. there are two outpout im pedance modes that the dacs can be operated in. th e first mode is the high impedance mode (low_imp bit set to 0). in this mode, the dac output driv es a double terminated 300 load and will output a video signal which conforms to the proper analog video specifications. external buffers will be needed if the dac output load differs from a double terminated 300 load. the second mode is th e low impedence mode (low_imp but set to 1). in this mode, the dac output drives a double terminated 75 load and will output a video signal which conforms to the proper analog video specifications. no external buffers are necessary. the ouputs can directly drive a television input. note that for power dissip ation purposes it is not always possible to have al l the 6 dacs active at the same time. table 8 shows the maximum number of active dacs allowed depe nding on the power sup- ply and low/high impedance modes. if less than 6 dacs are allowed to be active, the other dacs must be powered down (see control_4 regis- ter). 8. programming 8.1 host control interface the cs4954/5 host control interface can be config- ured for i2c or 8-bit parallel operation. the cs4954/5 will default to i2c operation when the rd and wr pins are both tied low at power up. the rd and wr pins are active fo r 8-bit parallel oper- ation only. 8.1.1 i2c ? interface the cs4954/5 provides an i2c interface for access- ing the internal control a nd status registers. exter- nal pins are a bidirecti onal data pin (sda) and a serial input clock (scl). the protocol follows the i2c specifications. a comp lete data transfer is shown in figure 26 . note that this i2c interface will work in slave mode only - it is not a bus mas- ter. sda and scl are connected via an external pull- up resistor to a positive supply voltage. when the bus is free, both lines ar e high. the output stages of devices connected to the bus must have an open- drain or open-collector in order to perform the wired-and function. data on the i2c bus can be transferred at a rate of up to 400 kbits/sec in fast mode. the number of interfac es to the bus is solely dependent on the limiting bus capacitance of 400 pf. when 8-bit parallel in terface operation is being used, sda and scl can be tied directly to ground. the i2c bus address for the cs4954/5 is program- mable via the i2c_adr register (00f). when i2c interface operation is being used, rd and wr nominal power supply low/high impedance mode maximum # of active dacs 3.3v low impedance 3 3.3v high impedance 6 5.0v low impedance 3 5.0v high impedance 6 table 8. maximum dac numbers
cs4954 cs4955 ds278f6 35 must be tied to ground. p dat [7:0] are available to be used for gpio operation in i2c host interface mode. for 3.3 v operation it is necessary to have the appropriate level shifting for i2c signals. 8.1.2 8-bit parallel interface the cs4954/5 is equipped wi th a full 8-bit parallel microprocessor write and read control port. along with the pdat [7:0] pins, the control port interface is comprised of host read (rd ) and host write (wr ) active low strobes and host address enable (addr), which, when low, enables unique address register accesses. the cont rol port is used to access internal registers which configure the cs4954/5 for various modes of operation. the internal registers are uniquely addressed via an address register. the address register is accessed during a host write cy- cle when the wr and addr pins set low. host write cycles with addr set high will write 8-bit data to the pdat [7:0] pins into the register cur- rently selected by the address register. likewise read cycles occuring with rd set low and addr set high will return the register contents selected by the address register. reference the detailed electri- cal timing parameter section of this data sheet for exact host parallel interface timing characteristics and specifications. sda scl a p start address 1-7 r/w 8 9 ack 1-7 data 89 1-7 8 9 ack data ack stop note: i2c transfers data a lways with msb first, lsb last figure 26. i2c protocol t rec t rec wr rd figure 27. 8-bit parallel host port timing: read-write/write-read cycle
cs4954 cs4955 36 ds278f6 8.2 register description a set of internal register s are available for control- ling the operation of the cs4954/5. the registers extend from internal a ddress 000 through 05a. table 9 shows a complete list of these registers and their internal addresses. no te that this table and the subsequent register descri ption section describe the full register map for the cs4954 only. a complete cs4955 register set description is available only to macrovision tm acp-ppv licensed buyers. 8.2.1 control registers padr rd pdat[7:0] t rd t rpw t rah t rda t rdh t as figure 28. 8-bit parallel host port timing: address read cycle wr padr pdat[7:0] t as t wds t wdh t wpw t wr t wac figure 29. 8-bit parallel host port timing: address write cycle address register name type default value 0 00 control_0 r/w 01h 0 01 control_1 r/w 02h 0 02 control_2 r/w 00h 0 03 control_3 r/w 00h 0 04 control_4 r/w 3fh 0 05 control_5 r/w 00h 0 06 control_6 r/w 00h 0 07 reserved 0 08 bkg_color r/w 03h table 9. control registers
cs4954 cs4955 ds278f6 37 0 09 gpio_ctrl_reg r/w 00h 0 0a gpio_data_reg r/w 00h 0 0b reserved 0 0c reserved 0 0d sync_0 r/w 90h 0 0e sync_1 r/w f4h 0 0f i2c_adr r/w 00h 0 10 sc_amp r/w 1ch 0 11 sc_synth0 r/w 3eh 0 12 sc_synth1 r/w f8h 0 13 sc_synth2 r/w e0h 0 14 sc_synth3 r/w 43h 0 15 hue_lsb r/w 00h 0 16 hue_msb r/w 00h 0 17 sch phase adjust r/w 00h 0 18 cc_en r/w 00h 0 19 cc_21_1 r/w 00h 0 1a cc_21_2 r/w 00h 0 1b cc_284_1 r/w 00h 0 1c cc_284_2 r/w 00h 0 1d reserved 0 1e wss_reg_0 r/w 00h 0 1f wss_reg_1 r/w 00h 0 20 wss_reg_2 r/w 00h 0 21 reserved 0 22 cb_amp r/w 80h 0 23 cr_amp r/w 80h 0 24 y_amp r/w 80h 0 25 r_amp r/w 80h 0 26 g_amp r/w 80h 0 27 b_amp r/w 80h 0 28 bright_offset r/w 00h 0 29 ttxhs r/w a1h 0 2a ttxhd r/w 02h 0 2b ttxovs r/w 00h 0 2c ttxove r/w 00h 0 2d ttxevs r/w 00h 0 2e ttxeve r/w 00h 0 2f ttx_dis1 r/w 00h 0 30 ttx_dis2 r/w 00h 0 31 ttx_dis_3 r/w 00h 0 32 int_en r/w 00h 0 33 int_clr r/w 00h address register name type default value table 9. control registers (continued)
cs4954 cs4955 38 ds278f6 control register 0 address 0 00 control_0 read/write default value = 01h control register 1 address 0 01 control_1 read/write default value = 02h 0 34 status_0 read only 0 35 - 0 59 reserved 0 5a status_1 read only 04h 0 61 - 0 7f reserved bit number 76543210 bit name tv_fmt mstr ccir656 prog in_mode cbcr_uv default 00000001 bit mnemonic function 7:5 tv_fmt selects the tv display format 000: ntsc-m ccir601 timing (default) 001: ntsc-m rs170a timing 010: pal-b, d, g, h, i 011: pal-m 100: pal-n (argentina) 101: pal-n (non argentina) 110-111: reserved 4mstr 1 = master mode, 0 = slave mode 3 ccir656 video input is in itu r.bt656 format with embedded eav and sav (0 = off, 1 = on) 2prog progressive scanning enable (enable = 1) 1 in_mode input select (0 = solid back ground, 1 = use v [7:0] data) 0 cbcr_uv enable ycbcr to yuv conversion (1 = enable, 0 = disable) bit number 76543210 bit name lum del ch bw lpf_on rgb_bw fld ped cbcrsel default 00000010 bit mnemonic function 7:6 lum del luma delay on the composite1 output 00: no delay (default) 01: 1 pixel clock delay 10: 2 pixel clock delay 11: 3 pixel clock delay address register name type default value table 9. control registers (continued)
cs4954 cs4955 ds278f6 39 5ch bw chroma lpf bandwidth (0 = 650 khz, 1 = 1.3 mhz) 4lpf on chroma lpf on/off (0 = off, 1 = on) 3rgb_bw 0 = full bandwidth on rgb, 1 = bw reduced to 2.5 mhz (3 db point) (default 0) 2fld_pol polarity of field (0: odd field = 0,1: odd field = 1) 1 ped pedestal offset (0: 0 ire, 1: 7.5 ire) 0 cbcrsel cbcr select (0 = chroma undelayed, 1 = chroma delayed by one clock) bit mnemonic function
cs4954 cs4955 40 ds278f6 control register 2 address 0 02 control_2 read/write default value = 00h bit number 76543210 bit name output format ttx wst ttx en sync_dly xtal sc_en default 00000000 bit mnemonic function 7:5 output format selects the output through the dacs 000 : rgb, s-video, compos ite1 (6 dacs) (default) 001 : yuv, s-video, composite1 (6 dacs) 010 : s-video, composite1, composite2, (4 dacs) 011 : rgb, composite1, composite2 (5 dacs) 100 : yuv, composite1, composite2 (5 dacs) 101-111: don?t care 4ttx wst to select between world standard (ntsc), world standard (pal), or north american teletext standard during ntsc or pal modes (1 = wst ttx) (default is 0) in ntsc-m or pal-m mode. this bit works in conjunction with the tv format register. 0: nabts, if tv format is ntsc or pal-m 1: wst (ntsc), if tv format is ntsc or pal-m 0: europe ttx, if tv format is pal-b, g..., n 1: wst (pal), if tv format is pal-b, g, ..., n 3ttx en enable teletext process (1 = enable) 2 sync dly slave mode 1 pixel sync delay (1 = enable) 1xtal crystal oscillator for subcarrier adjustment enable (1 = enable) 0bu dis chroma burst disable (1 = disable)
cs4954 cs4955 ds278f6 41 control register 3 address 0 03 control_3 read/write default value = 00h control register 4 address 0 04 control_4 read/write default value = 3fh note: 1. the field pin (pin 9) remain s an output pin in slave mode. however, the field pin state does not toggle in slave mode and its output state should be co nsidered random. bit number 76543210 bit name reserved fd thr c1 fd thr c2 fd thr sv fd thr en cbar default 00000000 bit mnemonic function 7:5 - reserved 4fd thr c1 feedthrough enabled for composite 1 output (0 = off, 1 = on) 3fd thr c2 feedthrough enabled for composite 2 output (0 = off, 1 = on) 2fd thr sv feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on) 1fd thr_en enable (1 = enable) input to feed through during inactive lines 0 cbar internal color bar generator (0 = off, 1 = on) bit number 7 6 5 4 3 210 bit name cb_h_sel cb_fld_sel (1) comdac_pd svidlum_pd svidchr_pd r_pd g_pd b_pd default 0 0 1 1 1 111 bit mnemonic function 7 cb_h_sel composite blank / hsync output select (1 = cb select, 0 = hsync select) 6 cb_fld_sel composite blank / field output select (1 = cb select, 0 = field select) (1) 5 comdac_pd power down composite dac 0: power up, 1: power down 4 svidlum_pd power down luma s-video dac 0: power up, 1: power down 3 svidchr_pd power down chroma s-video dac 0: power up, 1: power down 2r_pd power down red rgb video dac 0: power up, 1: power down 1g_pd power down green rgb video dac 0: power up, 1: power down 0b_pd power down blue rgb video dac 0: power up, 1: power down
cs4954 cs4955 42 ds278f6 control register 5 address 0 05 control_5 read/write default value = 00h control register 6 address 0 06 control_6 read/write default value = 00h bit number 76543210 bit name rsvd low imp en com en len cen ren gen b default 00000000 bit mnemonic function 7- reserved 6low imp selects between tri-state output (0) or output enabled (1) mode of dacs 5en com enable composite (cvbs) dac 0: high-impedance, 1: enable 4en l enable s-video y dac for luma out put 0: high-impedance, 1: enable 3en c enable s-video c dac for chroma output 0: high-impedance, 1: enable 2en_r enable rgb video r dac for red output 0: high-impedance, 1: enable 1en_g enable rgb video g dac for green ou tput 0: high-im pedance, 1: enable 0en_b enable rgb video b dac for blue output 0: high-impedance, 1: enable bit number 76543210 bit name 656 sync out clip off ttxen com2 ttxen com1 ttxen svid bsync dis gsync dis rsync dis default 00000000 bit mnemonic function 7 656 sync out enable (=1) output of hsync and vsync when in itu r.bt656 mode 6clip off clipping input signals disable (0: c lipping active 1: no clipping) 5 ttxen com2 enable teletext at the composite 2 output (0: disable teletext, 1 : enable teletext) 4 ttxen com1 enable teletext at the composite 1 output ( 0: disable teletext, 1 : enable teletext) 3 ttxen svid enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext) 2 bsync dis disable syncs in the blue or v output (0: enable syncs, 1: disable syncs) 1gsync dis disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs) 0 rsync dis disable syncs in the red or y output (0: enable syncs, 1: disable syncs)
cs4954 cs4955 ds278f6 43 background color register address 0 08 bkg_color read/write default value = 03h gpio control register address 0 09 gpio__reg read/write default value = 00h gpio data register address 0 0a gpio_reg read/write default value = 00h sync register 0 address 0 0d sync_0 read/write default value = 90h bit number 76543210 bit name bg default 00000011 bit mnemonic function 7:0 bg background color (7:5 = r, 4:2 = g, 1:0 = b) (default is 0000 0011 - blue) bit number 76543210 bit name gpr_cntrl default 00000000 bit mnemonic function 7:0 gpr cntrl input(0)/output(1) control of gpio regist ers (bit 0: pdat(0), bit 7: pdat(7)) bit number 76543210 bit name gpio reg default 00000000 bit mnemonic function 7:0 gpio reg gpio data register ( data is output on pdat bus if appropriate bit in address 09 is set to ?1?, otherwise data is input/output th rough i2c)- this register is only accessible in i2c mode. bit number 76543210 bit name prog vs[4:0] prog hs[10:8] default 10010000 bit mnemonic function 7:3 prog vs[4:0] programmable vsync lines 2:0 prog hs[10:8] programmable hsync pixels (3 most significant bits)
cs4954 cs4955 44 ds278f6 sync register 1 address 0 0e sync_1 read/write default value = f4h i2c address register address 0 0f i2c_adr read/write default value = 00h subcarrier amplitude register address 0 10 sc_amp read/write default value = 1ch subcarrier synthesis register address 0 11 sc_synth0 read/write default value = 3eh 0 12 sc_synth1 f8h 0 13 sc_synth2 e0h 0 14 sc_synth3 43h bit number 76543210 bit name prog hs[7:0] default 11110100 bit mnemonic function 7:0 prog hs[7:0] programmable hsync pixels lsb bit number 76543210 bit name reserved i2c adr default 00000000 bit mnemonic function 7- reserved 6:0 i2c i2c device address (programmable) bit number 76543210 bit name bu amp default 00011100 bit mnemonic function 7:0 bu amp color burst amplitude register bits mnemonic function sc_synth0 7:0 cc 0 subcarrier synthesis bits 7:0 sc_synth1 7:0 cc 1 subcarrier synthesis bits 15:8 sc_synth2 7:0 cc 2 subcarrier synthesis bits 23:16 sc_synth3 7:0 cc 3 subcarrier synthesis bits 31:24
cs4954 cs4955 ds278f6 45 hue lsb adjust register address 0 15 hue_lsb read/write default value = 00h hue msb adjust register address 0 16 hue_msb read/write default value = 00h sch sync phase adjust address 0 17 sch read/write default value = 00h closed caption enable register address 0 18 cc_en read/write default value = 00h bit number 76543210 bit name hue lsb default 00000000 bit mnemonic function 7:0 hue lsb 8 lsbs for hue phase shift bit number 76543210 bit name reserved msb default 00000000 bit mnemonic function 7:2 - reserved 1:0 hue msb 2 msbs for hue phase shift bit mnemonic function 7:0 sch adjust in increments of 1.4 degree per bit up to 360 bit number 765432 1 0 bit name reserved en_284 en_21 default 000000 0 0 bit mnemonic function 7:2 - reserved 1 cc en[1] enable closed caption for line 284 0 cc en[0] enable closed caption for line 21
cs4954 cs4955 46 ds278f6 closed caption data register address 0 19 cc_21_1 read/write default value = 00h 0 1a cc_21_2 00h 0 1b cc_284_1 00h 0 1c cc_284_2 00h wide screen signaling register 0 address 0 1e wss_reg_0 read/write default value = 00h bit mnemonic function 7:0 cc_21_1 first closed caption databyte of line 21 7:0 cc_21_2 second closed caption databyte of line 21 7:0 cc_284_1 first closed caption databyte of line 284 7:0 cc_284_2 second closed caption databyte of line 284 bit number 765432 1 0 bit name wss_23 wss_22 wss_21 wss_20 wss_19 wss_18 wss_17 wss_16 default 000000 0 0 bit mnemonic function 7 wss_23 enable wide screen si gnalling (enable =1) 6 wss_22 pal: enable wss (enable = 1) on line 23 of field 2, ntsc: don?t care 5 wss_21 pal: group 4, bit 13, ntsc: don?t care 4 wss_20 pal: group 4, bit 12, ntsc: don?t care 3 wss_19 pal: group 4, bit 11, ntsc: bit 20 2 wss_18 pal: group 3, bit 10, ntsc: bit 19 1 wss_17 pal: group 3, bit 9, ntsc: bit 18 0 wss_16 pal: group 3, bit 8, ntsc: bit 17
cs4954 cs4955 ds278f6 47 w ide screen signa lling register 1 address 0 1f wss_reg_1 read/write default value = 00h wide screen signalling register 2 address 0 20 wss_reg_2 read/write default value = 00h f ilter register 0 address 0 22 cb_amp read/write default value = 80h bit number 765432 1 0 bit name wss_15 wss_14 wss_13 wss_12 wss_11 wss_10 wss_9 wss_8 default 000000 0 0 bit mnemonic function 7 wss_15 pal: group 2, bit 7, ntsc: bit 16 6 wss_14 pal: group 2, bit 6, ntsc: bit 15 5 wss_13 pal: group 2, bit 5, ntsc: bit 14 4 wss_12 pal: group 2, bit 4, ntsc: bit 13 3 wss_11 pal: group 1, bit 3, ntsc: bit 12 2 wss_10 pal: group 1, bit 2, ntsc: bit 11 1 wss_9 pal: group 1, bit 1, ntsc: bit 10 0 wss_8 pal: group 1, bit 0, ntsc: bit 9 bit number 765432 1 0 bit name wss_7 wss_6 wss_5 wss_4 wss_3 wss_2 wss_1 wss_0 default 000000 0 0 bit mnemonic function 7 wss_7 pal: don?t care, ntsc: bit 8 6 wss_6 pal: don?t care, ntsc: bit 7 5 wss_5 pal: don?t care, ntsc: bit 6 4 wss_4 pal: don?t care, ntsc: bit 5 3 wss_3 pal: don?t care, ntsc: bit 4 2 wss_2 pal: don?t care, ntsc: bit 3 1 wss_1 pal: don?t care, ntsc: bit 2 0 wss_0 pal: don?t care, ntsc: bit 1 bit number 76543210 bit name u_amp default 10000000 bit mnemonic function 7:0 u_amp u(cb) amplitud e coefficient
cs4954 cs4955 48 ds278f6 f ilter register 1 address 0 23 cr_amp read/write default value = 80h f ilter register 2 address 0 24 y_amp read/write default value = 80h f ilter register 3 address 0 25 r_amp read/write default value = 80h f ilter register 4 address 0 26 g_amp read/write default value = 80h bit number 76543210 bit name v_amp default 10000000 bit mnemonic function 7:0 v_amp v(cr) amplitude coefficient bit number 76543210 bit name y_amp default 10000000 bit mnemonic function 7:0 y_amp luma amplitude coefficient bit number 76543210 bit name r_amp default 10000000 bit mnemonic function 7:0 r_amp red amplitude coefficient bit number 76543210 bit name g_amp default 10000000 bit mnemonic function 7:0 g_amp green amplitude coefficient
cs4954 cs4955 ds278f6 49 f ilter register 5 address 0 27 b_amp read/write default value = 80h f ilter register 6 address 0 28 bright_offsett read/write default value = 00h teletext register 0 address 0 29 ttxhs read/write default value = a1h t eletext register 1 address 0 2a ttxhd read/write default value = 02h bit number 76543210 bit name b_amp default 10000000 bit mnemonic function 7:0 b_amp blue amplitude coefficient bit number 76543210 bit name brightness_offset default 00000000 bit mnemonic function 7:0 brght_offset brightness adjustment ( range: -128 to +127) bit number 76543210 bit name ttxhs default 10100001 bit mnemonic function 7:0 ttxhs start of teletext request pulses or start of window bit number 76543210 bit name ttxhd default 00000010 bit mnemonic function 7:0 ttxhd if ttx_window = 0 then this register is used as the pipeline delay between ttxrq and ttxdat signals in the teletext source. user programmable delay step of 37 ns per lsb. if ttx_window = 1 then this register is used as the 8 lsbs of the teletext insertion windows; the 3 msbs are located in register 031. (register 031 bit 3)
cs4954 cs4955 50 ds278f6 teletext register 2 address 0 2b ttxovs read/write default value = 00h t eletext register 3 address 0 2c ttxove read/write default value = 00h teletext register 4 address 0 2d ttxevs read/write default value = 00h t eletext register 5 address 0 2e ttxeve read/write default value = 00h bit number 76543210 bit name ttxovs default 00000000 bit mnemonic function 7:0 ttxovs start of teletext line window in odd field bit number 76543210 bit name ttxove default 00000000 bit mnemonic function 7:0 ttxove end of teletext line window in odd field bit number 76543210 bit name ttxevs default 00000000 bit mnemonic function 7:0 ttxevs start of teletext line window in even field bit number 76543210 bit name ttxeve default 00000000 bit mnemonic function 7:0 ttxeve end of teletext line window in even field
cs4954 cs4955 ds278f6 51 teletext register 6 address 0 2f ttx_dis1 read/write default value = 00h t eletext register 7 address 0 30 ttx_dis2 read/write default value = 00h t eletext register 8 address 0 31 ttx_dis3 read/write default value = 00h bit number 76543210 bit name ttx_line_dis1 default 00000000 bit mnemonic function 7:0 ttx_line_dis1 teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all eight lines are disabled), (msb is for line 5, lsb is for line 12) bit number 76543210 bit name ttx_line_dis2 default 00000000 bit mnemonic function 7:0 ttx_line_dis2 teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all eight lines are disabled, (msb is for line 13, lsb is for line 20) bit number 765 4 3 210 bit name ttxhd reserved ttx_window ttx_line_dis3 default 000 0 0 000 bit mnemonic function 7:5 ttxhd if ttx_window = 0 these 3 bits are unused. if ttx_window = 1 these 3 bits are the msbs of the register 02a; they are used to specify the length of the teletext insertion window 4 reserved 3ttx_window selects between ttxrq (= 0) pulsation or ttxrq (= 1) window mode 2:0 ttx_line_dis3 teletext disable bits corresponding to th e lines 13-20 respectively, (111=all three lines are disabled), (msb is for line 21, lsb is for line 23)
cs4954 cs4955 52 ds278f6 interrupt register 0 address 0 32 int_en read/write default value = 00h interrupt register 1 address 0 33 int_clr read/write default value = 00h status register 0 address 0 34 status_0 read only default value = 00h status register 1 address 0 5a status_1 read only default value = 04h bit number 76543 2 1 0 bit name reserved int_21_en int_284_en int_v_en default 00000 0 0 0 bit mnemonic function 7:3 - reserved 2 int_21_en interrupt enable for closed caption line 21 1 int_284_en interrupt enable for closed caption line 284 0int_v_en interrupt enable for new video field bit number 76543 2 1 0 bit name reserved clr_int_21 clr_int_284 clr_int_v default 00000 0 0 0 bit mnemonic function 7:3 - reserved 2 clr_int_21 clear interrupt for closed caption line 21 (int 21) 1 clr_int_284 clear interrupt for closed caption line 284 (int_284) 0 clr_int_v clear interrupt for new video field (int_v) bit number 543 2:0 bit name int_21 int_284 int_v fld default 000 0 bit mnemonic function 5int_21 interrupt flag for line 21 (closed caption) complete 4 int_284 interrupt flag for line 284 (closed caption) complete 3int_v interrupt flag for video field change 2:0 fld_st field status bits(001 = field 1,000 = field 8) bit number 76543210 bit name device_id default 00000100 bit mnemonic function 7:0 device_id device identification: cs4954: 0000 0100, cs4955: 0000 0101
cs4954 cs4955 ds278f6 53 9. board design and layout considerations the printed circuit layout should be optimized for lowest noise on the cs4954/5 placed as close to the output connectors as possible. all analog supply traces should be as short as possible to minimize in- ductive ringing. a well designed power dist ribution network is es- sential in eliminating di gital switching noise. the ground planes must provide a low-impedance re- turn path for the digital ci rcuits. a pc board with a minimun of four layers is recommended. the ground layer should be used as a shield to isolate noise from the analog traces. the top layer (1) should be reserved for analog traces but digital traces can share this layer if the digital signals have sufficiently slow edges a nd edge rates and switch little current or if they are separated from the ana- log traces by a signigicant distance (dependent on their frequency content a nd current). the pcb lay- er ?stack up? (from top to bottom) should be: ana- log/digital signal then ground plane followed by the analog power plane and the digital signal layer. 9.1 power and ground planes the power and ground planes need isolation gaps of at least 0.05 " to minimize digital switching noise effects on the analog signa ls and components. a split analog/digital gr ound plane should be con- nected at one location as close as possible to the cs4954/5. 9.2 power supply decoupling start by reducing power supply ripple and wiring harness inductance by pl acing a large (33-100 uf) capacitor as close to the power entry point as pos- sible. use separate power planes or traces for the digital and analog sections even if they use the same supply. if necessary, fu rther isolate the digital and analog power supplies by using ferrite beads on each supply branch foll owed by a low esr capac- itor. place all decoupling caps as close as possible to the device. surface mount ca pacitors generally have lower inductance than radial lead or axial lead com- ponents. surface mount caps should be place on the component side of the p cb to minimize inductance caused by board vias. a ny vias, especially to ground, should be as large as possible to reduce their inductive effects. 9.3 digital interconnect the digital inputs and outputs of the cs4954/5 should be isolated from the analog outputs as much as possible. use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. noise from the digital secti on is related to the digi- tal edge rates and rise /fall times. ringing, over- shoot, undershoot, a nd ground bounce are all related to edge rise/fall times. use lower speed log- ic such as hcmos for the host port interface to re- duce switching noise. for the video input ports, higher speed logic is re quired, but use logic that produces the slowest practi cal edge rise/fall times to reduce noise. it is also important to match the source impedance, line impedance, and load im- pedance as much as possibl e. generally, if the line length is greater than one fourth of the signal wave- length or period (from = / f), a line termination is necessary. ringing can also be reduced by damping the line with a seri es resistor (22-150 ). under ex- treme cases, it may be a dvisable to use microstrip techniques to further re duce radiated switching noise if there are very fast (<2 ns) rise/fall times in the system. if microstrip techniques are used, split the analog and digital gr ound planes and use proper rf decoupling techniques. 9.4 analog interconnect the cs4954/5 should be locat ed as close as possi- ble the output connectors to minimize noise pickup and reflections due to im pedance mismatch. all un- used analog outputs should be placed in shutdown.
cs4954 cs4955 54 ds278f6 this reduces the total power that the cs4954/5 re- quires, and eliminates the impedance mismatch presented by an unused connector. the analog out- puts should not overlay th e analog power plane in order to maximize high fr equency power supply re- jection. 9.5 analog output protection to minimize the possibility of damage to the ana- log output secti ons, make sure th at all video con- nectors are well grounde d. the connector should have a good dc ground path to the analog and dig- ital power supply grounds. if no dc (and low fre- quency) path is present, improperly grounded equipment can impose damaging reverse currents on the video out lines. therefore, it is also a good idea to use output filters that are ac coupled to avoid any problems. 9.6 esd protection all mos devices are sens itive to electro static discharge (esd). when manipulating these devic- es, proper esd precauti ons are recommended to avoid performance degrad ation or permanent dra- mage. 9.7 external dac output filter if an output filt er is required, the low pass filter shown in figure 30 can be used. 2.2 h 330pf 220pf out in c 1 c 2 figure 30. external low pass filter note: c 2 should be chosen so that c 1 = c 2 + c cable 33pf
cs4954 cs4955 ds278f6 55 figure 31. typical connection diagram ferrite bead l1 vcc 17 36 41 38 39 40 43 44 48 47 12 34 37 18 35 42 45 15 14 16 30 31 26-19 27 28 32 33 29 8 8-1 9 10 11 13 xtalin xtalout paddr ttxdat ttxrq pdat[7:0] rd wr sda scl clk v[7:0] field hsync vsync gnda y c cvbs red green blue int i2c controller vcc vaa vref composite video 75 or 300 ? 75 or 300 ? s-video connector 75 or 300 ? 4k 1% /cb test 27 mhz clock pixel data 110 110 1.5 k 1.5 k gpio port nc 4.7 f 0.1 f 300 ? 300 ? 300 ? cs4954 75 or 75 or 75 or /cb to scart connector iset 46 gndd vdd cs4955 reset int connector * identical load resistors are to be used at the receive device.
cs4954 cs4955 56 ds278f6 10. pin description b cvbs gnda vaa c y v0 v1 v2 v3 v4 v5 v6 v7 field /cb hsync /cb vsync int test xtal_out xtal_in padr vdd gndd gnda vaa g r vref iset vaa gnda reset scl sda ttxrq ttxdat clkin wr rd pdat0 pdat1 pdat2 pdat3 pdat4 pdat5 pdat6 pdat7 CS4955-CQZ 48-pin tqfp top view 48 47 46 45 44 43 41 42 40 39 38 37 13 14 15 16 17 18 20 19 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 cs4954-cqz
cs4954 cs4955 ds278f6 57 note: 1. the field pin (pin 9) remain s an output pin in slave mode. however, the field pin state does not toggle in slave mode and its output state should be co nsidered random. pin name pin number type description v [7:0] 8, 7, 6, 5, 4, 3, 2, 1 in digital video data inputs clk 29 in 27 mhz input clock paddr 16 in address enable line xtal_in 15 in subcarrier crystal input xtal_out 14 out subcarrier crystal output hsync /cb 10 i/o active low horizontal sync , or composite blank signal vsync 11 i/o active low vertical sync. field/cb (1) 9out (1) video field id. selectable polarity or composite blank rd 27 in host parallel port read strobe, active low wr 28 in host parallel port write strobe, active low pdat [7:0] 19, 20, 21, 22, 23, 24, 25, 26 i/o host parallel port/ general purpose i/o sda 32 i/o i2c data scl 33 in i2c clock input cvbs 44 current composite video output y 48 current luminance analog output c 47 current chrominance analog output r 39 current red analog output g 40 current green analog output b 43 current blue analog output vref 38 i/o internal voltage reference output or external reference input iset 37 current dac current set ttxdat 30 in teletext data input ttxrq 31 out teletext request output int 12 out interrupt output, active high reset 34 in active low master reset test 13 in test pin. ground for normal operation vaa 36, 41, 46 ps + 5 v or + 3.3 v supply (must be same as vdd) gndd 18 ps ground vdd 17 ps +5 v or 3.3 v supply (must be same as vaa) gnda 35, 42, 45 ps ground table 10. device pin description s
cs4954 cs4955 58 ds278f6 11. package drawing inches millimeters dim min max min max a --- 0.063 --- 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.343 0.366 8.70 9.30 d1 0.272 0.280 6.90 7.10 e 0.343 0.366 8.70 9.30 e1 0.272 0.280 6.90 7.10 e* 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l tqfp package drawing e1 e d1 d 1 e l b a1 a
cs4954 cs4955 ds278f6 59 12. revision history revision date change f1 july 1999 initial release f2 april 2004 corrected list of figures f3 september 2004 added lead free package option (cs4955). f4 august 2005 updated ordering information. added lead -free package for cs4954; deleted cq packages; updated revision history and legal notice. f5 july 2006 - changed operating temperature range in ?description? on page 1 to -40 to 85 c - changed operating temperature range in ?recommended operating condi- tions? on page 6 - changed operating temperature range in ?ordering information? on page 2 . - changed allowable junction temperature specification and added note to ?ther- mal characteristics? on page 6 - revised description in ?progressive scan? on page 18 . - revised descriptions in ?luminance dac? on page 32 , ?chrominance dac? on page 33 , ?cvbs dac? on page 33 , ?red dac? on page 33 , ?green dac? on page 33 and ?blue dac? on page 33 . - added ?dac useage rules? on page 34 and revised text in that section. - revised bit 3 ?function? description for ?control register 0? on page 38 . - revised ?function? descriptions for ?control register 5? on page 42 . - added note to clarify dac loading to figure 31 on page 55 . - revised text throughout the document to correct content and grammar. f6 september 2006 added ?this port can operate in standard (up to 100 kb/sec) or fast (up to 400 kb/sec) modes? in section 4.10 on page 14. updated scl frequency values in timing characteristics table on page 9.
cs4954 cs4955 60 ds278f6 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus produc ts are not designed, authorized or warranted for use in aircraft systems, milita ry applications, products surgic ally implanted into th e body, automoti ve safety or security de- vices, life support products or other critical appl ications. inclusion of cirrus pro ducts in such applic ations is under- stood to be fully at the customer?s risk and cirrus disc laims and makes no warranty, express, statutory or implied, including the implied warranties of mercha ntability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permit s the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, em ployees, dist ributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. macrovision is a trademark of macrovision corporation. it is he reby notified that a third-party license from macrovision corpor ation is necessary to distribute software of macrovision corporation in any finished end-user or ready-to-use final product.

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